Field of the Invention
The present invention generally relates to integrated circuit chip packaging. More particularly, the present invention relates to integrated circuit chip packaging connecting an integrated circuit chip to a conductive layer embedded between layers of a printed circuit board.
Description of the Related Art
Conventional methods and systems for connecting an integrated circuit chip to a printed circuit board have relied upon a surface attachment. A surface attachment restricts the launch to a conductive layer that is on the surface of a printed circuit board and if a signal from the integrated circuit chip must be launched into a conductive layer that is between the layers of the printed circuit board (i.e., an embedded conductor), then the signal is subject to problems, which may be caused by vias that are used to transfer the signal from the surface to the embedded conductor.
Conventionally, an integrated circuit chip may be placed into a carrier (e.g., a package) and the carrier may then be mounted onto a surface of the printed circuit board. Exemplary conventional techniques are shown in FIG. 1.
FIG. 1 shows a conventional surface mount package 102 and a conventional flip chip package mounting 104. The conventional flip chip package mounting 104 connects to the printed circuit board using two via configurations. A first configuration includes a via 106 that has a long stub 107 that extends past an embedded conductor layer 108. The flip chip 104 is electrically connected to the embedded conductor layer 108.
The second configuration includes a buried via 110 that does not include a lengthy stub and, therefore, avoids the signal degradation associated with a lengthy stub. However, a buried via 110 is more expensive to fabricate. The conventional surface mount package 102 also shows connection to another embedded conductor 111, which connects to the distal end of via 109. This configuration, referred to as a “through via,” minimizes the length of the stub, but the presence of the via still leads to signal distortion.
In addition, if many signals try to connect to embedded conductors at the same level of a layer, then wiring congestion may result.
Integrated circuit chips that operate at high frequencies often rely on flip chip packaging to minimize the parasitics that are associated with conventional chip packages. For best performance, conventionally, the highest speed signals use conductive surface layers or buried vias in the printed circuit board in order to reduce a via stub effect that may compromise signal transmission.